1. Field of the Invention
The invention concerns a controlled oscillator and more particularly an output driver stage for such an oscillator, providing a 50% duty cycle output signal. A driver is also well known and referred to as a buffer.
2. Discussion of the Related Art
FIG. 1 illustrates a partial schematic and partial circuit diagram of an output driver stage for use with an asymmetrical current controlled oscillator as described in the European patent application 93420390.2.
Referring to FIG. 1, an adjustable current source S1 having its high side connected to a positive voltage supply rail VDD supplies, via its low side 5, the high side of a three stage ring oscillator 10. The current source S1 is adjusted by a frequency control signal 8.
The ring oscillator 10 comprises three CMOS inverters 20. The high side of each inverter is connected to the low side 5 of the current source S1. The low side of each inverter is connected to a negative supply rail VSS.
The output of each inverter 20, starting with the left-most inverter, is connected to the input of the succeeding inverter. The output 25 of the right-most inverter is connected to the input of the left-most inverter. Thus, an unbroken ring 10 of three inverters is created.
The current source S1 and the ring oscillator 10 are connected together in such a manner that they form an asymmetrical current controlled oscillator 30.
An output buffer 35 comprises a P-MOS and an N-MOS transistor, respectively MP5 and MN5. The source terminals of transistors MP5 and MN5 are respectively connected to the positive supply rail VDD and the negative supply rail VSS, and their drain terminals are connected together to form the output terminal 40 of the buffer 35. The gate terminal of transistor MN5 is connected to the output 25 of the ring oscillator 10, whereas the gate terminal of transistor MP5 is connected to the frequency control signal 8 of the adjustable current source S1.
An asymmetrical current controlled oscillator 30 is differentiated from a symmetrical current controlled oscillator in that the ring oscillator 10 has either a high side current source or a low side current sink but not both, in contrast to a symmetrical current controlled oscillator.
One advantage of the asymmetrical current controlled oscillator 30, as illustrated in FIG. 1, is that the oscillator inverters 20 produce lower switching noise, in the form of a voltage variation, at the terminal 5 to which the current source S1 is connected. This is due to the fact that not all of the inverters 20 are switching at the same time; therefore, the current source S1 is continually supplying current to the inverters 20. Reduced switching noise results in a superior quality output signal 25.
Another advantage of the asymmetrical current controlled oscillator 30 is that a low supply voltage, approximately 3V, can be applied, thus reducing the power loss and increasing efficiency.
With an output stage of the type illustrated in FIG. 1, the duty cycle of the CMOS compatible output signal 40 can vary considerably over the oscillator's large operating frequency. This is disadvantageous because in certain applications, a relatively constant value of the duty cycle of the output signal is important.
The ring oscillator 10 can be designed so that its output 25 has a relatively constant duty cycle of approximately 50% over its entire operating frequency range. The variation in the duty cycle is attributed to the output buffer 35. The signal at the output 40 of the buffer 35 will have a duty cycle of less than 50% when the oscillator's operating frequency is high and a duty cycle greater than 50% when the oscillator's operating frequency is low. The reason for the variation in the duty cycle stems from the fact that the amount of current sourced by transistor MP5 is modulated as a function of the operating frequency of the oscillator 10, yet the current sinking capabilities of transistor MN5 is fixed, and the load connected to the output 40 is also fixed. The more current sourced by transistor MP5, the quicker its load switches and the less time it needs to be on.